The present invention pertains to a semiconductor memory device. More specifically, it pertains to a semiconductor memory device which reads stored data by switching output signals from plural sense amplifiers.
A method in which the number of memory cells connected to bit lines is increased is presented as a relatively simple method for increasing the storage capacity of a semiconductor memory device, such as an SRAM. However, the capacitive constituents of the memory cells increase with the number of memory cells, and the capacitive constituents of the bit lines also increase as they become longer, creating the problem that the memory cells driving the bit lines are more heavily loaded. Because the driving capability of a transistor utilized for a memory cell is subject to limits imposed by the type of manufacturing process, the use of said method to increase the storage capacity is thereby also limited.
Thus, a method in which the number of bit lines is increased is widely used as another method for increasing the storage capacity.
FIG. 7 is a block diagram of an example configuration of a semiconductor memory device in which the number of bit lines is increased light times.
The semiconductor memory device shown in FIG. 7 has memory cell array 1, bit line selector circuit 2, and sense amplifier 3.
Memory cell array 1 has memory cells arranged in rows and columns, and the memory cells in respective columns are connected to bit line pairs (BL0, BL0Z) through (BL7, BL7Z). Although not shown specifically, memory cells in each row are connected to a common word line, and access is gained to memory cells connected to an activated word line via applicable bit line pair (BL0, BL0Z) through (BL7, BL7Z).
Bit line selector circuit 2 selects among bit line pairs (BL0, BL0Z) through (BL7, BL7Z) according to bit line selection signal SEL0Z through SEL7Z and outputs the signals on the selective bit line pair to sense amplifier 3.
In the example illustrated in FIG. 7, bit line selector circuit 2 has p-type MOS transistors 2-0 through 2-7 and p-type MOS transistors 2-0Z through 2-7Z.
Bit lines BL0 through BL7 on one side of the bit line pairs are connected to common output line N, and bit lines BL0Z through BL7Z on the other side are connected to common output line NZ. In addition, p-type MOS transistors 2-0 through 2-7 are inserted into the connecting lines between bit lines BL0 through BL7 and output line N, and p-type MOS transistors 2-0Z through 2-7Z are inserted into the connecting lines between bit lines BL0Z through BL7Z and output line NZ. Bit line selection signals SEL0Z through SEL7Z are input to the gates of p-type MOS transistors 2-0 through 2-7, and bit line selection signals SEL0Z through SEL7Z are input also to the gates of p-type MOS transistors 2-0Z through 2-7Z.
Sense amplifier 3 amplifies the small difference in voltage of bit line pair selected by bit line selector circuit 2 during a read of data stored in the memory cells. The value of the data stored in a memory cell is identified on the basis of said amplified voltage difference.
In the case of the semiconductor memory device in FIG. 7, to read the data stored in the memory cells, one of bit line selection signals SEL0Z through SEL7Z is set to a low level according to the address to be read. Thus, the p-type MOS transistor which received the low-level bit line selection signal through its gate conducts, and the signal from one of bit line pairs (BL0, BL0Z) through (BL7, BL7Z) is output to sense amplifier from output line N and NZ 3 via the conducting p-type MOS transistor.
On the other hand, when a word line of memory cell array 1 is activated in response to said read address, bit line pair (BL0, BL0Z) through (BL7, BL7Z) is driven by the memory cells connected to the activated word line, and the voltage difference corresponding to the data stored in the memory cell is generated on bit line pair (BL0, BL0Z) through (BL7, BL7Z).
Sense amplifier 3 amplifies the voltage difference on the single bit line pair from the bit line pairs selected by bit line selector circuit 2, and the value of the stored data is identified on the basis of said voltage difference.
Thus, with the semiconductor memory device in FIG. 7, the memory capacity can be increased by selecting I bit line pair from the plural bit line pairs using the selector circuit. However, the aforementioned method has the problem that the selector circuit itself used for bit line selection loads the memory cells. For example, the capacitive constituents of p-type MOS transistors 2-1 through 2-7 of bit line selector circuit 2 are also added to the capacitive constituents of the memory cells as the load of bit line BL0 of the semiconductor memory device in FIG. 7. As the number of the bit line pairs is further increased, the load due to the capacitive constituents of the transistors of the selector circuit increases.
Thus, as the number of the bit line pairs is increased, often the method is used in which plural bit line selector circuits and plural sense amplifiers are used, with the output signals being switched.
FIG. 8 is a block diagram illustrating an example configuration of a semiconductor memory device in which the number of the bit lines is increased by 16 times using 2-bit line selector circuits and sense amplifiers.
The semiconductor memory device shown in FIG. 8 has memory cell array 1, bit line selector circuits 2_A and 2_B, sense amplifiers 3_A and 3_B, latch circuits 4_A and 4_B, and switch circuits 5_A and 5_B.
Memory cell array 1A has plural memory cells arranged in rows and columns, and 16 columns of memory cells are connected to 16 bit line pairs. Said 16 bit line pairs are divided into 2 blocks, each comprising 8 pairs, one of the 2 blocks (referred to as Block A hereinafter) is connected to bit line selector circuit 2_A, and the other (referred to as Block B hereinafter) is connected to bit line selector circuit 2_B.
In addition, like memory cell array 1, memory cells in each row are connected to a common word line, and the memory cells are accessed by activating specific word lines and bit line pairs.
Bit line selector circuit 2_A selects 1 bit line pair out of the 8 bit line pairs of Block A according to bit line selection signal SB and outputs the signals on the selected bit line pair to sense amplifier 3_A.
Bit line selector circuit 2_B selects 1 bit line pair out of the 8 bit line pairs of Block B according to bit line selection signal SB and outputs the signals on the selected bit line pair to sense amplifier 3_B.
Said bit line selector circuits 2_A and 2_B can be configured using a circuit similar to bit selector circuit 2 of the semiconductor memory device in FIG. 7.
Sense amplifier 3_A amplifies the small difference in the voltage of bit line pair selected by bit line selector circuit 2_A when enable signal EN (not shown) changes from low level to high level during a read of the stored data. Since said voltage difference is amplified, either output terminal SA_A or SAZ_A is set to the high level, and the other is set to the low level.
Sense amplifier 3_B amplifies the small difference in the voltage of bit line pair selected by bit line selector circuit 2_B when enable signal EN (not shown) changes from the low level to the high level during a read of stored data. Since said voltage difference is amplified, either output terminal SA_B or SAZ_B is set to the high level, and the other is set to the low level.
Said amplification operation is performed by one of the 2 sense amplifiers 3_A or 3B, whichever is selected according to block selection signal line SM.
Latch circuit 4_A outputs a high-level or low-level signal SL_A to switch circuit 5_A according to the levels of signals of output terminals SA_A and SAZ_A of sense amplifier 3_A. When output terminals SA_A and SAZ_A are both at the high level, the level of output signal SL_A is held.
Latch circuit 4_B outputs a high-level or low-level signal SL_B to switch circuit 5_B according to the levels of signals of output terminals SA_B and SAZ_B of sense amplifier 3_B. When output terminals SA_B and SAZ_B are both at the high level, the level of output signal SL_B is held.
Switch circuit 5_A and switch circuit 5_B are connected to a common output terminal, wherein, one of the switch circuits, the one selected by block selection enable signal SMEN, is turned on, and the other switch circuit is turned off. The signal latched by latch circuit 4_A is output when switch circuit 5_A is turned on, or the signal latched by latch circuit 4_B is output when switch circuit 5_B is turned on, and sent to the common output terminal as read signal SAOUT from a memory cell.
The operation of the semiconductor memory device in FIG. 8 will be explained with reference to the timing diagram in FIG. 9.
In the timing diagram in FIG. 9, Block B of the 2 bit line pair blocks is selected by block selection signal SM (FIG. 9A) and block selection enable signal SMEN (FIG. 9E) in the initial stage. Thus, switch circuit 5_B is turned on, and high-level signal latched by latch circuit 4_B is output as read signal SAOUT (FIG. 9F). In addition, because the input terminal of sense amplifier 3_A has been charged to the power supply voltage by a precharger not illustrated, output terminals SA_A and SAZ_A (FIG. 9C) are both at the high level. Output signal SL_A (FIG. 9D) of latch circuit 4_A is kept at the high level.
Once a new address for reading data is set at time ta, bit line selection signal SB and block selection signal SM are updated. In the case of the example in FIG. 9, the selection of a block based on block selection signal SM (FIG. 9A) changes from Block B to Block A. In addition, 1 of the word lines of memory cell array 1A is activated in response to the setting of said new read address, the bit line pair is driven by the memory cells connected to the activated word line, and a voltage difference corresponding to the data stored in the memory cells is generated on the bit line pair.
Once enable signal EN changes from the low level to the high level at time tb, sense amplifier 3_A selected based on block selection signal SM begins the amplification operation, wherein, output terminal SA_A changes to the low level, and output terminal SAZ_A changes to the high level. Upon receiving said changes in the levels of the output terminals, output signal SL_A (FIG. 9D) of latch circuit 4_A changes from the high level to the low level at time tc. When the block selection is changed from Block B to Block A according to block selection enable signal SMEN (FIG. 9E) at time td, that is, when appropriate time margin Tm has passed after time tc, switch circuit 5_A is turned on, switch circuit 5_B is turned off, and low-level signal latched by latch circuit 4_A is output as output signal SAOUT.
With the semiconductor memory device in FIG. 8, while the number of the transistors of the bit line selector circuit that acts as a load to the bit lines remains the same as that of the semiconductor memory device in FIG. 7, the number of the memory cells can be doubled compared with the semiconductor memory device in FIG. 7.
However, in the case of the semiconductor memory device in FIG. 8, time margin Tm must be provided so as to fully assure output signals SL_A and SL_B of latch circuits 4_A and 4_B prior to the selection of a latch circuit by block selection enable signal SMEN in order to prevent an invalid signal from appearing as output signal SAOUT. Therefore, disadvantageously, the access speed decreases in proportion to said time margin Tm. Also disadvantageously, because the timing of block selection enable signal SMEN must be controlled to match the requirement of time margin Tm, a suitable circuit must be added for this purpose.
The present invention was conceived in light of the foregoing problems, and its purpose is to present a semiconductor memory device with which the access time can be further improved and the aforementioned memory capacity can be increased without increasing the loading of the bit lines.
In order to solve the aforementioned problems, the semiconductor memory device of the present invention is provided with a memory cell array containing plural memory cells which are arranged in the form of a matrix between plural bit line pairs divided into plural blocks each comprising a prescribed number of bit line pairs and plural word lines, plural bit line selector circuits which are provided in correspondence to the aforementioned respective plural blocks so as to select 1 bit line pair from the aforementioned prescribed number of bit line pairs and electrically connect said selected bit line pair to an output line pair, plural bit line charge circuits which charge each of the aforementioned plural output line pairs to a prescribed signal level, plural amplifier circuits that amplify the difference in the signal levels generated on the aforementioned respective plural output line pairs according to data stored in the selected memory cell, a block selector circuit which selects one of the aforementioned plural output line pairs provided in correspondence to the aforementioned plural blocks according to a block selection signal and electrically connects said selected output line pair to a selectable output line pair, and a data latch circuit which latches output data when the signal level of the aforementioned selectable output line pair is not a complementary signal level and outputs first data or second data corresponding to the complementary signal level, either a first or a second complementary signal level, indicated by the signal level of the aforementioned selectable output line pair.
The configuration may be such that the aforementioned block selector circuit has plural gate circuits connected respectively between the aforementioned plural output line pairs and the aforementioned selectable output line pair, and the aforementioned plural gate circuits comprise first and second switch circuits connected between one side of the aforementioned output line pair and the other side and between one side of the aforementioned selectable output line pair and the other side, respectively, in order to control the aforementioned first and the second switch circuits to conduct or not conduct according to a control signal.
Furthermore, the configuration may be such that the aforementioned plural bit line selector circuits have first and second data write circuits connected to one side and the other side of the aforementioned prescribed number of bit line pairs, and the aforementioned first and the second data write circuits supply complementary signals to one side and the other side of the aforementioned bit line pair in response to a write signal.